Freescale Semiconductor /MKL28T7_CORE1 /USB0 /OTGISTAT

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as OTGISTAT

7 43 0 0 00 0 0 0 0 0 0 0 0 (LINE_STATE_CHG)LINE_STATE_CHG 0 (ONEMSEC)ONEMSEC

Description

OTG Interrupt Status register

Fields

LINE_STATE_CHG

This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits) are stable without change for 1 millisecond, and the value of the line state is different from the last time when the line state was stable

ONEMSEC

This bit is set when the 1 millisecond timer expires

Links

() ()